Type-C and USB PD
* Supports USB PD3.0 protocol and PPS
* RP and RD with configurable CC ports
* Supports 2 Type-C ports for independent PD communication
* CC port supports 21 V withstand voltage
* 2 built-in high-voltage (21 V) control ports
* Supports fast role switching (FRS)
Other protocols
* Supports QC4.0+, SCP, FCP, and AFC protocols
* Supports the OPPO VOOC protocol
* Supports BC1.2 and Apple 2.4A
* Supports all configurations on DP and DM
* Supports multiple fast charging protocol inputs, such as FCP and AFC
Peripherals
Up to 27 general-purpose (GPIO) pins
3 – 16-bit timers, 8-bit pre-scaled
1 group of UARTs
1 group of SPIs
1 group of I2C (supports the master-slave mode)
2 analog comparators
12-bit analog-to-digital converter (ADC)
11-bit digital-to-analog converter (DAC)
Brown-out detection (BOD)
32-bit MCU
ARM® Cortex™-M0 core. The main frequency is up to 48 MHz
60 K Flash memory is used to save application programs (APROM)
Configurable data flash
4 KB boot code space (LDROM)
Embedded 8 KB SRAM
Configurable system boot interval, boot from APROM, LDROM, or SRAM
Clock and crystal
24/8 MHz internal oscillator (HSI) (25 °C, 5 V, error: 1%)
10 kHz internal low-power oscillator (LSI)
Operating mode: (Low-power mode, multi-clock low-power strategy)
Normal mode, operating current: 10 mA @ 5 V, 25 °C
Sleep mode, operating current: 2 mA @ 5 V, 25 °C
Deep-Sleep1 mode, operating current: 100 uA @ 5 V, 25 °C
Deep-Sleep2 mode, operating current: 12 uA @ 5 V, 25 °C
Deep Power-Down mode, operating current: 2.5 uA @ 5 V, 25 °C
Chip security
Provide a multi-level security policy for flash memory
Provide a CRC-32 calculation unit. The polynomial is 0 x 4C11DB7 (same as the Ethernet standard)
Built-in SRAM supports parity check
Operating conditions
Operating temperature: -40 °C –85 °C
Operating voltage: 2.5 V–5.5 V